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Low Skew, 1-to-4 LVCMOS/LVTTL-to-LVDS Fanout Buffer
ICS8545I-02
DATASHEET
General Description
The ICS8545I-02 is a low skew, high performance 1-to-4 LVCMOS/LVTTL-to-LVDS Clock Fanout Buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8545I-02 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100. The ICS8545I-02 accepts an LVCMOS/LVTTL input level and translates it to 3.3V LVDS output levels.
Features
* * * * * * * * * * *
Four differential LVDS output pairs Two LVCMOS/LVTTL clock inputs to support redundant or selectable frequency fanout applications Maximum output frequency: 350MHz Translates LVCMOS/LVTTL input signals to LVDS levels Output skew: 60ps (maximum) Part-to-part skew: 450ps (maximum) Propagation delay: 1.45ns (maximum) Additive phase jitter, RMS: 0.14ps (typical) Full 3.3V supply mode -40C to 85C ambient operating temperature Available in lead-free (RoHS 6) package
ICS
Guaranteed output and part-to-part skew characteristics make the ICS8545I-02 ideal for those applications demanding well defined performance and repeatability.
Block Diagram
CLK_EN Pullup nD Q LE CLK1 Pulldown CLK2 Pulldown CLK_SEL Pulldown 0 0 1 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 OE Pullup
Pin Assignment
GND CLK_EN CLK_SEL CLK1 nc CLK2 nc OE GND VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDD Q1 nQ1 Q2 nQ2 GND Q3 nQ3
ICS8545I-02 20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body G Package Top View
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Table 1. Pin Descriptions
Number 1, 9, 13 2 Name GND CLK_EN Power Input Pullup Type Description Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects CLK2 input. When LOW, selects CLK1 input. LVCMOS / LVTTL interface levels. Single-ended clock input. LVCMOS/LVTTL interface levels. No connect. Pulldown Pullup Single-ended clock input. LVCMOS/LVTTL interface levels. Output enable. Controls enabling and disabling of outputs Q0/nQ0 through Q3/nQ3. LVCMOS/LVTTL interface levels. Positive supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
3 4 5, 7 6 8 10, 18 11, 12 14, 15 16, 17 19, 20
CLK_SEL CLK1 nc CLK2 OE VDD nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0
Input Input Unused Input Input Power Output Output Output Output
Pulldown Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
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Function Tables
Table 3A. Control Input Function Table
Inputs OE 0 1 1 1 1 CLK_EN X 0 0 1 1 CLK_SEL X 0 1 0 1 CLK1 CLK2 CLK1 CLK2 Selected Source Q0:Q3 High-Impedance Low Low Active Active Outputs nQ0:nQ3 High-Impedance High High Active Active
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK1 and CLK2 inputs as described in Table 3B.
Disabled
Enabled
CLK1, CLK2
CLK_EN
nQ[0:3] Q[0:3]
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs CLK1 or CLK2 0 1 Q0:Q3 LOW HIGH Outputs nQ0:nQ3 HIGH LOW
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuos Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 91.1C/W (0 mps) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 90 Units V mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK1, CLK2, CLK_SEL OE, CLK_EN CLK1, CLK2, CLK_SEL OE, CLK_EN VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 150 5 Units V V A A A A
IIL
Table 4C. LVDS DC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Symbol VOD VOD VOS VOS Parameter Differential Output Voltage VOD Magnitude Change Offset Voltage VOS Magnitude Change 1.1 1.25 5 Test Conditions Minimum 275 Typical Maximum 525 50 1.4 50 Units mV mV V mV
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AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 3.3V 5%, TA = -40C to 85C
Symbol fMAX tPD tjit tsk(o) tsk(pp) tR / tF odc Parameter Output Frequency Propagation Delay; NOTE 1 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Skew; NOTE 2, 4 Part-to-Part Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle; NOTE 5 20% to 80% 166MHz > 166MHz 150 45 40 155.52MHz, Integration Range: 12kHz - 20MHz 1.0 0.14 60 450 700 55 60 Test Conditions Minimum Typical Maximum 350 1.45 Units MHz ns ps ps ps ps % %
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Measured using 50% duty cycle.
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz 12kHz to 20MHz = 0.14ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment.
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Parameter Measurement Information
VDD
SCOPE
3.3V5% POWER SUPPLY + Float GND -
VDD
Qx
nQ0:nQ3
V
PP
LVDS
nQx
Q0:Q3
Cross Points
V
CMR
GND
3.3V LVDS Output Load AC Test Circuit
Differential Output Level
Par t 1
nQx Qx nQy Qy
nQx Qx
Par t 2
nQy Qy
tsk(pp)
tsk(o)
Part-to-Part Skew
Output Skew
nQ0:nQ3 Q0:Q3 CLK1, CLK2
t PW
t
PERIOD
nQ0:nQ3 Q0:Q3
odc =
t PW t PERIOD
x 100%
tPD
Output Duty Cycle/Pulse Width/Period
Propagation Delay
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Parameter Measurement Information, continued
VDD
nQ0:nQ3

80%
80% VOD
out
Q0:Q3
20% tR tF
20%
DC Input
LVDS
100
VOD/ VOD out
Output Rise/Fall Time
Differential Output Voltage Setup
VDD out
DC Input
LVDS
out
VOS/ VOS
Offset Voltage Setup
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Application Information
Recommendations for Unused Input and Output Pins Inputs:
CLK Inputs
For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from the CLK input to ground.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, there should be no trace attached.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs.
3.3V 3.3V 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
Figure 2. Typical LVDS Driver Termination
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Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8545I-02. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8545I-02 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 90mA = 311.85mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 91.1C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.312W * 91.1C/W = 113.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
Table 6. Thermal Resistance JA for 20 Lead TSSOP, Forced Convection
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 91.1C/W 1 86.7C/W 2.5 84.6C/W
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Reliability Information
Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP
JA by Velocity Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 91.1C/W 1 86.7C/W 2.5 84.6C/W
Transistor Count
The transistor count for ICS8545I-02 is: 360
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions
All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153
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Ordering Information
Table 9. Ordering Information
Part/Order Number 8545AGI-02LF 8545AGI-02LFT Marking ICS8545AI02L ICS8545AI02L Package "Lead-Free" 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
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ICS8545I-02 Data Sheet
LOW SKEW, 1-TO-4 LVCMOS/LVTTL-TO-LVDS FANOUT BUFFER
6024 Silver Creek Valley Road San Jose, California 95138
Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT
Technical Support netcom@idt.com +480-763-2056
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 2009. All rights reserved.

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